Master Trainer : Mr. David Vallet

Date : 6-7^th July 2012 ( Friday & Saturday )

Location : Singapore

 

Who Should Attend :

This course is designed for test and debug personnel, failure analysts, and characterization, yield, and reliability analysis engineers, technicians, managers, and anyone who submits devices to, performs, or analyzes results from failure analysis laboratories. Researchers, developers, and vendors of fault isolation and related equipment and failure analysis tooling in general will also benefit.

 

COURSE OUTLINE

Microelectronic and now nanoelectronic failure analysis has become increasingly challenging with higher density packaging, transistor counts into the billions, scaling below 45 nanometers, and new materials. This course examines both traditional and recently developed tools and techniques for isolating and identifying defects on simple and advanced ICs and microelectronic packages.

 

A complete overview of the failure analysis process will be introduced before providing specific details on the many electrical, physical, mechanical, and chemical techniques for characterizing, isolating, examining and identifying defects. Methodologies for AC and DC parametric, cache, and logic failures in package and die level devices are discussed. Numerous case histories will be shown and technique capabilities and limitations examined along with challenges and future outlook.

 

Abstracts

•         The role of failure analysis in semiconductor development and manufacturing

•         Characterization and preparation for failure analysis

•         Electrical fault isolation principles and techniques (e.g. nanoprobing, time-domain

          reflectometry)

•        Physical fault isolation principles and techniques (e.g., electron, ion, magnetic,

          photon emission, and laser scanning microscopy)

•         Chemical, mechanical, and ion beam deprocessing

•         Optical, acoustic, scanned probe, electron, and X-ray microscopy and

          tomography

•         Basic chemical and materials analysis

•         Memory, logic, analog, and mixed signal device approaches

•         Wafer and die level analytical strategies

•         Unique challenges of 3D packaging failure analysis

•         Technology development, yield, reliability, and customer return failures and

          defects

•         Case-histories and examples

•         Planning for analysis to maximize effectiveness scaling and material challenges

          in IC analytical science

 

About Mr. David Vallet

 

Mr. David Vallett has almost 30 years experience in CMOS characterization and failure analysis. He is with the Technology Quality Analytical Services organization in IBM’s Systems and Technology Group. He is widely published with four best-paper awards and has given a number of lectures on analytical technology challenges in both micro and nanoelectronics. He holds fourteen US patents and shared in IBM's Outstanding Technical Achievement award for his contributions to picosecond imaging circuit analysis (PICA) using time-resolved photon emission microscopy.

 

Mr. Vallett is a senior member of the IEEE, a member of the Electronic Device Failure Analysis Society board of directors, and belongs to Tau Beta Pi - the National Engineering Honor Society. He is a past chair of the International SEMATECH Product Analysis Forum and served as the 2008 General Chair for ISTFA - the International Symposium for Testing and Failure Analysis.

 

His presently manages the department responsible for technology development and packaging failure analysis, silicon machining, nanoprobing, X-ray tomography, and physical fault isolation using magnetic field, photon emission, and laser scanning microscopy. Mr. Vallett holds the BS degree in electrical engineering from the University at Buffalo, New York, USA.

 

Click HERE to register for course.