|DFT For Complex Asic & SoC|
Design For Test of Complex ASIC & SoC
Master Trainer : Dr. Chouki Aktouf
Date : 10th Sept 2012
Location : Singapore
Target Audience : DFT Engineer, Digital IC Design Engineer, Test Engineer
o Be familiar with Industrial Design For Test flows and solutions
o Understand differences between structural Testing and Functional Testing
o Get a basic knowledge of the ATPG process: test pattern generation, fault simulation, fault modeling, etc.
o Get basic background of mainstream DFT methodologies and techniques : Built-In Self-Test, Internal scan, Boundary scan (IEEE 1149.1, iJTAG), Test compression, Test point insertion, etc.
o Existing DFT methodologies and solutions at Register Transfer Level
o Analyze a case study which covers main concepts
· Morning Session
§ Preliminaries & basic concepts
§ Test Economics basics
§ Test process & fault models et modèles de fautes
§ Structural testing vs. functional testing
· Typical example of DFT flow
· Discussion & Technical Interaction
· Afternoon Session
§ Methodologies and Advanced DFT flows
§ Case study presentation and analysis
§ Discussion & Technical interaction
· Final Session
§ Conclusions & Technical interaction
About Dr Chouki Aktouf
Dr. Chouki Aktouf is founder and CEO of DeFacTo Technologies which specializes in developing EDA solution to better handle DFT implementation and testing in RTL level. Prior to setting up DeFacTo, he was associate professor at the university of Grenoble (France), and tea, manager at the Laboratory of Design and Integration of Systems at the National Polytechnic Institute of Grenoble (INPG). He obtained his PhD in electrical engineering from INPG in 1995 and is currently a member of IEEE.
Between 1991 and 2005, Dr Chouki Aktouf has developed and supervised the development of VLSI courses at the INPG and has directed projects in VLSI design, Design for Test of VLSI chips and also in networking. He also found in France the first training center in collaboration with CISCO. He has provided more than 10 training sessions to companies of different sizes in France in the domain of “Testing & Design For Test of VLSI chips”. Last but not least, he has authored tens of IEEE papers and several book chapters in VLSI design and DFT of VLSI chips.
Click HERE to register for course.